1. Field of the Invention
The invention relates to a method of defining polysilicon patterns and more particularly, to a method of etching a polysilicon layer.
2. Description of the Prior Art
As technology progresses in semiconductor fields, it is a trend that N-poly and P-poly process integration is used to obtain different electric gate structures to satisfy the various needs of the semiconductor elements. Because the N-poly and P-poly areas have different dopings, they have different results in the process, such as the development of the line width of the semiconductor elements, the profile of the N-poly and P-poly, the after etch-inspection critical dimension (AEI CD), and uniformity of the etched gate oxide layer (GOX). Thus, it is important to provide an ideal method to define the N/P polysilicon patterns, approximate the profile and AEI CD of the N-poly and P-poly, and have enough thickness of the GOX after etching GOX.
Please refer to FIG. 1 and FIG. 2 that are schematic diagrams for defining polysilicon patterns according to prior art. As shown in FIG. 1, the method provides a substrate 10 and sequentially forms a gate oxide layer 12, a polysilicon layer 14, and a patterned mask 16 on the substrate 10. The polysilicon layer 14 includes a doping polysilicon layer 14a defined as a N-poly, and a non-doping polysilicon layer 14b defined as a P-poly, and the mask 16 is a photoresist layer or hard mask.
As shown in FIG. 2, an etching process is performed to remove a portion of the polysilicon layer 14 not covered by the mask 16. Because the etching rate of the doping polysilicon layer 14a is far faster than that of the non-doping polysilicon layer 14b, the sidewalls of the doping polysilicon layer 14a haveside cuts 18 so that the profile and AEI CD of N-poly cannot approximate the P-poly.
Please refer to FIG. 3 and FIG. 4 that are schematic diagrams for further defining polysilicon patterns according to prior art. As shown in FIG. 3, the method provides a substrate 30 and sequentially forms a gate oxide layer 32, a polysilicon layer 34, and a patterned mask 36 on the substrate 30. The polysilicon layer 34 includes various areas defined as N-poly and P-poly (not shown), a non-doping polysilicon layer 34a, and a doping polysilicon layer 34b formed on the non-doping polysilicon layer 34a. In addition, the mask 36 is a photoresist layer or hard mask.
As shown in FIG. 4, an etching process is performed to remove a portion of the polysilicon layer 34 not covered by the mask 36. Because the etching rate of the doping polysilicon layer 34b is far faster than that of the non-doping polysilicon layer 34a, the sides of the doping polysilicon layer 34b have side cuts 38.
Therefore, the applicant proposes a method of defining polysilicon patterns that can approximate the profile and AEI CD of the N-poly with the P-poly and make a large GOX pitting window to enhance the uniformity of the polysilicon patterns.